Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

System, PCB, & Package Design 

Simulation for a Song: Downloading Models from the Web and Associating with Parts…

While on a long drive, I like to sing along; say Eye of the Tiger or Johny B Goode…

• 3 min read
capture , Models , PSPICE , OrCAD , simulation

Analog/Custom Design

Virtuosity: Virtuoso ADE Verifier in IC6.1.8 and ICADVM18.1 – Better, Faster, Further…

Cutting-edge innovation … Top-down planning … Reliable and formalized verification…

• 3 min read
verifier , PVT , ICADVM18.1 , custom/analog , Formalized Verification , Analog Simulation , ADE , Virtuoso Analog Design Environment , Virtuoso , Virtuosity , space , Custom IC Design , ADE Verifier , IC6.1.8 , ADE Assembler , verification

Breakfast Bytes

60 Years of DARPA—61 Actually

On 4th August 1957, the Soviet Union launched the first artificial satellite, Sputnik…

• 5 min read
Aerospace , magestic , arpa , space , eri , darpa , chips

Analog/Custom Design

Virtuoso IC6.1.8 ISR1 and ICADVM18.1 ISR1 Now Available

The IC6.1.8 ISR1 and ICADVM18.1 ISR1 production releases are now available for download…

• 2 min read
Analog Design Environment , ICADVM18.1 , ADE Explorer , Virtuoso Space-based Router , ADE , Layout , Virtuoso , cadenceblogs , IC Release Blog , New in EDA , Virtuoso: The Next Overture , Custom IC Design , Virtuoso Layout Suite , Custom IC , IC6.1.8

Breakfast Bytes

DesignCon 2019

It doesn't seem to matter what a show is ostensibly about at the moment. Every show…

• 4 min read
uber , DesignCon , AMI , IBIS , 112g , photonics

定制IC芯片设计

Virtuosity: 如何使用ADE Explorer 及ADE Assembler 打开旧版本的ADE 状态和视图文件

您是否发现，当您查看 Virtuoso ® ADE L 状态（State）文件，或者 Virtuoso ® ADE XL 视图 (View) 文件时，默认打开程序仍然是旧版本的…

• 1 min read
Chinese blog , Analog Design Environment , Virtuoso ICADVM18.1 , ICADVM18.1 , ADE Explorer , ADE Migration , maestro , ADE , Virtuoso IC6.1.8 , Virtuoso ADE Explorer , Virtuoso ADE Assembler , IC6.1.8 , ADE Assembler

Breakfast Bytes

Emerging Memories Poised to Explode

A couple of weeks ago was the Persistent Memory Summit. (For more details, see my…

• 5 min read
fram , ReRAM , flash , xpoint , 3D NAND , NAND flash , emerging memories , DRAM , nor flash , MRAM , PCRAM

Breakfast Bytes

DesignCon: Cadence Teaches AMI and IBIS

At the recent DesignCon, Cadence and customer IBM presented a tutorial on Advanced…

• 9 min read
DesignCon , AMI , IBIS , SerDes

PCB、IC封装：设计与仿真分析

2019七大行业动向预测

本文翻译自Cadence “Breakfast Bytes”专栏作者Paul McLellan文章 “ Breakfast Nibbles: Predictions…

• less than a min read
5G , Chinese blog , 内存 , 无人车 , 3nm , 电动车 , DRAM , 中文 , 汽车 , 云 , 5nm , 神经网络 , AI , EUV

Breakfast Bytes

Sunday Brunch Video for 3rd February 2019

https://youtu.be/CXTltDRjb-M Made at DesignCon 2019 (camera Sean) Monday: IEDM:…

• less than a min read
5G , DFT , Memory , CES , modus , mobile , persistent memory , IEDM

Breakfast Bytes

Programming Persistent Memory

I talked earlier this week about the recent persistent memory summit (see my post…

• 5 min read
programming model , persistent memory

Analog/Custom Design

Virtuosity: Simulation Planning and Coverage Environment (SPACE)- Introduction

An important requirement for project sign-off is to ensure that all the design simulations…

• 2 min read
verifier , PVT , coverage , Analog Coverage , Analog Simulation , Virtuoso Analog Design Environment , space , Custom IC Design , Assembler , verification

Breakfast Bytes

Persistent Memory

Last week was the latest Persistent Memory Summit. In the semiconductor world, we…

• 8 min read
persistence , Intel , non-volatile , persistent memory summit , ReRAM , optane , MRAM , persistent memory , 3dxpoint

Breakfast Bytes

What Next for Modus DFT?

I sometimes say that test is the red-headed stepchild of EDA, that doesn't get the…

• 3 min read
modus , Test , scantest

Verification

Specman is Sweet – Bosch Sensortec's Story

Recently, Bosch Sensortec has been using Specman for their functional verification…

• 1 min read
Specman , Bosch , e , success

Breakfast Bytes

CES: 5G, All Hat and No Cattle

Increasingly, CES seems to be less about consumer electronics, and more about the…

• 9 min read
5G , mmwave , CES , MWC

Analog/Custom Design

Virtuosity: Introducing the Pin Tool

The Pin Tool follows an object-based approach to working with pins by consolidating…

• 2 min read

Life at Cadence

Empowered to Support Our Community

Cadence understands that the success of our business, our employees, and the community…

FormerMember • 2 min read
Insights on Culture , giving back , Fortune 100 best companies to work for , great place to work

Verification

New Training Bytes Available Now: All About SystemVerilog Classes

If you’re leaving 2018 with the feeling that your SystemVerilog skills are lacking…

• 2 min read
SystemVerilog , Functional Verification , classes , training , training bytes
CDNS - Fix Layout Hompage