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Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent

Corporate News

AI Infrastructure Starts Beyond the Chip

Why Advanced Packaging and PCB Design Have Become the Next Frontier of Innovation…

Corporate
• 8 min read
chip , featured , AI infrastructure , agentic ai , packaging

Digital Design

Cadence RTL Design Studio: Built for the Full PPAC Journey

If you've used Joules RTL Design Studio, you already know what it can do. Now it…

raquelp
• 2 min read
Digital Design and Signoff , featured , Joules , Digital Implementation , rtlstudio

Corporate News

How the New ASK AI Assistant Makes Support More Seamless

Finding the right answer often takes more than one question. Users may start with…

Corporate
• 2 min read
featured , customer support , Generative AI , ASK Portal , ASK AI Assitant
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Analog/Custom Design

Green, Red, and Blue Lights in the Layout Design — What Do They Indicate?

As you know, even after generating the layout from the source, there can still be…

• 4 min read
visual bind , unbind , Cadence blogs , Virtuoso Studio , custom/analog , cadence , analog , Layout EXL , bind , Layout Suite , training bytes , Layout , Virtuoso , swap , analog design , Custom IC Design , bind color map , online training , Virtuoso Layout Suite EXL , Virtuoso Layout Suite , Binder , Custom IC , binding

Verification

ONFI 5.2: What’s new in Open NAND Flash Interface's latest 5.2 standard

Non-volatile memories like Nand Flash are key components of most modern system-on…

• 3 min read
Verification IP , non-volatile memory , flash , ONFT5.2 Vs ONFI5.1 , ONFI , VIP , memory models , ONFI5.2 , NAND , sca

Life at Cadence

Building Bridges Through Education and Innovation

This fall, a group of 11 Cadence employees from Brazil, Germany, India, Italy, the…

• 2 min read
featured , Cadence Cares , giving back , Employee Volunteerism

Cloud

A New Era of Cadence Managed Cloud Service

The Future of Secure, Scalable EDA in the Cloud As the semiconductor industry accelerates…

• 2 min read
Managed Cloud , OnCloud Marketplace , EDA , cadence cloud , cloud eda

Corporate News

2.5D vs 3D-IC: Architecture Tradeoffs, and a Practical Selection

As traditional scaling slows and multi-die integration becomes the new engine of…

• 5 min read
architecture , 3D-IC , advanced packaging , vertical stacking , 3D-IC Technology , 2.5D

Computational Fluid Dynamics

Reduce Noise and Improve Fan Performance with Serrated Edges

Understanding Noise Reduction in Industrial Fans Industrial fans are widely utilized…

• 4 min read
CFD , fan performance , turbomachinery , serrated edges , Industrial Fans , simulation software

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

• 1 min read
news story , Verification IP , featured

カスタムIC／ミックスシグナル

Virtuoso Studio: 快適な作業環境 - 新しいディスプレイテーマや可読性の向上

これは、Virtuoso Studio IC 25.1のリフレッシュに関する5部構成のブログシリーズの第2弾です。IC設計における日々の作業をより快適で目に優しいものにするため…

• 1 min read
Cadence blogs , Virtuoso Studio , japanese blog , Custom IC Design

The India Circuit

Story of Suraj Gaur - Cadence Scholarship Program

In the bustling lanes of Faridabad, just beyond Delhi’s metroscape, Suraj Gaur quietly…

• 1 min read
CadenceCares , CadenceScholarshipProgram , cadence , Cadence India

Verification

Powering Up Efficiency: A Deep Dive into CXL L0p and its Verification

Compute Express Link (CXL) is revolutionizing data center architecture, with power…

• 3 min read
CXL , performance , Verification IP , Functional Verification , coherent , l0p

Digital Design

From FOMO to PPA: Catch Up on Low-Power Design with Genus Synthesis Solution!

Did you miss the “ Introduction to Low-Power Optimization with Genus Synthesis Solution…

• 3 min read
low-power technique , webinar , optimization , training bytes , Genus Synthesis Solution , online training , Training Webinar

Computational Fluid Dynamics

Making Every RPM Count with Fidelity CFD

As the need for miniaturization, efficiency, and accelerated design processes intensifies…

• 4 min read
CFD , Fidelity Autogrid , Fidelity Optimization , turbomachinery , ENTECHMACH

Corporate News

3D-IC Design Tools: Cadence Workflows for Planning, Assembly, and Analysis

3D-IC design tools are becoming increasingly essential as the industry transitions…

• 6 min read
celsius , Virtuoso Studio , Tempus , Integrity 3D-IC Platform , 3D-IC , Voltus , Sigrity , Innovus Implementation , Allegro , clarity

Analog/Custom Design

Virtuoso Studio: Viewing Designs Clearly - Understanding LPP Transparency

Virtuoso Studio introduces LPP Transparency—a feature that gives you clearer visibility…

• 3 min read
Cadence blogs , Virtuoso Studio , Custom IC Design , Custom IC

Corporate News

Cadence, NVIDIA, and Solar Turbines Collaborate on AI Physics

Accelerated computing and advanced simulation technologies are changing the game…

• 4 min read
CFD , LLM , ai physics , model , simulation

Corporate News

What Is 3D-IC Technology? Fundamentals, Architecture, and Design Concepts

As process nodes continue to advance into the sub-micron era, the limitations of…

• 5 min read
Integrity 3D-IC Platform , chiplet , 3D-IC , advanced packaging , vertical stacking , 3D-IC Technology

Cadence Japan

ケイデンス、ChipStack社を迎えAI駆動型のチップ設計・検証を加速

ケイデンスはChipStack社を迎えることで、エージェント型AIソリューションを強化します。生成AI駆動型プラットフォームとXcelium、Jasperの統合により…

• less than a min read
ChipStack , agentic ai , Xcelium Logic Simulator , AI-Driven Verification , japanese blog

Corporate News

Jasper User Group 2025: A Recap of Innovations and Insights

The Jasper User Group 2025, the annual must-attend event for the formal community…

• 3 min read
Jasper User Group , Jasper Formal Verification Platform , GenAI , verification

Verification

Demystifying CXL Memory Interleaving and HDM Decoder Configuration

Memory interleaving is a technique that distributes memory addresses across multiple…

• 5 min read
CXL , Verification IP , VIP , PCIe
CDNS - Fix Layout Hompage