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Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA

Corporate News

Honda + Cadence = Physical AI (part 2): Where Physical AI Will Be Won

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The real challenge of physical…

Corporate
• 8 min read
featured , physical ai , HGR , AI , Honda

Corporate News

The New ASK Portal Brings a Smarter, Faster, and More Intuitive Experience

Finding the right support content should be simple, fast, and intuitive. The new…

Corporate
• 2 min read
featured , customer support , New ASK Portal , ASK Gen AI
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Blog - Post List
Latest blogs

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

• 4 min read
news story , Edge AI , featured , Ambarella

SoC and IP

Ensuring End-to-End Traceability for Safety-Critical Applications

There is now a direct interface between the Midas Safety Platform and popular requirements…

• 4 min read
Requirement Management System , Safety Solution , DOORS , functional safety , RMS , Safety , Product Lifecycle Management , Safety Analysis , JIRA , Traceability , Jama , Polarion , PLM , Codebeamer , Safety Compliance

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Verification

Evolution of AMBA AXI Protocol: An Introduction to the Issue L Update

To gain a comprehensive understanding of AMBA® AXI Issue L (AXI-L) protocol update…

• 3 min read
AXI , Verification IP

Verification

An Introduction to AMBA CHI Chip-to-Chip (C2C) Protocol

As chip designs grow larger and more complex, they become increasingly difficult…

• 2 min read
C2C , multi-die , chip-chip , AMBA , CHI VIP , verification

System, PCB, & Package Design 

BoardSurfers: Training Insights: Upskill Engineers using PCB Editor Basic Course

Are you seeking an effective and proven method to onboard and upskill new engineers…

• 4 min read
PCB , PCB Layout and routing , Routing , Allegro X PCB Editor , APD , Constraint Manager , via , PCB design , Allegro PCB Editor , allegro x , Schematic , Allegro

Corporate News

Vaire Computing – Near-Zero Energy Computing for Agentic AI

The demand for AI is on the rise, with agentic AI being the next frontier. However…

• 2 min read
agentic ai , designed with cadence

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

• 2 min read
IC 23.1 , Virtuoso Studio , IC Release , Virtuoso , IC Release Blog , Custom IC Design , Custom IC , IC design

Computational Fluid Dynamics

Addressing Secondary Flow Effects in Turbomachinery with Fidelity CFD

Secondary flows cause up to 50% of aerodynamic losses in turbines. This post explores…

• 5 min read
CFD , turbomachinery , Aachen turbine , Fidelity CFD , secondary flow

SoC and IP

Boosting AI Performance with CXL

AI workloads are outpacing traditional memory architectures—but CXL®︎ offers a smarter…

• 3 min read
CXL , Design IP , IP , controller , PCIe

SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

• 3 min read
ucie , Design IP , featured , TSMC , die-to-die , HPC , AI

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC , AI

Analog/Custom Design

Virtuoso Studio: Faster, Smarter Object Creation with Quick Dimension Editing

This blog introduces QDE, a feature that streamlines object creation. Instead of…

• 3 min read
Virtuoso Studio , Quick Dimension Edit , Virtuoso , Custom IC Design , QDE , Virtuoso Layout Suite , Custom IC , Virtuoso Layout Suite XL

System, PCB, & Package Design 

ALS Uses Cadence Sigrity X to Accelerate High-Speed PCB Design

A new Cadence success story details how Advanced Layout Solutions (ALS), a UK-based…

• 2 min read
PCB , Power Integrity , Signal Integrity , PCB design , Sigrity

Life at Cadence

A Day in the Life: HR Intern Edition

Written by Alisha Jain Every day as a Cadence intern brings something new – whether…

• less than a min read
Culture , featured , LifeAtCadence , great place to work , internship

Physical Systems Simulation (CAE)

How Multiphysics Is Transforming Product Design

This page was originally published as a part of Hexagon's Design and Engineering…

• 3 min read
physical systems simulation , computer-aided engineering , CAE Software , multiphysics

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

• 6 min read
Automotive , featured , physical ai , automotive electronics , AI

SoC and IP

Cadence Powers AI Infra Summit '25: Memory, Interconnect, and Interface Focus

AI is driving a new semiconductor renaissance—it's no longer just a workload, but…

• 2 min read
controller IP , ucie , Design IP , IP , Memory , AISummit , 224G-LR , HBM , hbm4 , memory IP , Ethernet , AI training , Ethernet PHYs , UALink , AI , data centers , AIInfraSummit

Digital Design

RTL-to-GDSII Back-End Flow: Navigating from Synthesis to Timing Signoff

Are you interested in learning the key steps to designing a physical layout from…

• 3 min read
Synthesis to Timing Signoff , Physical verification , conformal , DFT , design rule violations , online courses , Innovus Implementation System , Routing , LEC , STA , Setup and Hold Analysis , Cadence Online Support , Floorplanning , RTL-to-GDSII , training , webinar , place and route , Cadence training , RTL-to-GDSII BackEnd , Digital Implementation , Cadence Modus DFT , Timing analysis , Genus Synthesis Solution , Synthesis , signoff , silicon signoff , Tempus Timing Signoff Solution , online training , physical implementation , Cadence RTL2GDSII Flow , Modus ATPG , cadence learning and support
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