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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

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Latest blogs

System, PCB, & Package Design 

IC Packagers: 17.4-2019 Hotfix 019 Is Here! What Does That Mean?

The HotFix 019 of our 17.4-2019 release is available for download and installation…

• 5 min read
17.4 , IC Packaging , degassing , APD , IC Packaging & SiP design , Allegro Package Designer , 17.4-2019 , ICPackagers , Allegro

Computational Fluid Dynamics

Big Wave Surfboard Optimization Using Cadence's Pointwise and CRUNCH CFD

Stephen Barr, Roger Birkbeck, Jeremy ShipmanCombustion Research and Flow Technology…

• 13 min read
CFD , Marine Engineering , Pointwise , Computational Fluid Dynamics , fluid dynamics , Mesh Generation

Computational Fluid Dynamics

What Is Intern Reading Club?

As the summer winds down, interns are busy completing their assigned projects and…

• 4 min read
Interns , internships , soft skills , workplace skills

Digital Design

Conformal Low Power Verification

Learn to verify low-power designs using Conformal ® Low-Power Verification. We've…

FormerMember • less than a min read

Computational Fluid Dynamics

Cadence CFD at the SU2 Conference 2021

Last month's SU2 Conference brought together the community of researchers and practitioners…

• 3 min read
CFD , Automotive , T-Rex , Aerospace , Pointwise , automation , Computational Fluid Dynamics , voxels , adaptation , Mesh Generation

定制IC芯片设计

Virtuoso Meets Maxwell: Virtuoso RF Solution快速入门

不同种类的模组设计之间的集成趋势引起了PCB 设计风格的流程正向IC设计风格的流程转变。对于任何一个先进的模组设计流程而言，多芯片封装的跨结构设计和验证都必不可少…

• 1 min read
Rapid Adoption Kit , Virtuoso Meets Maxwell , Virtuoso System Design Environment , Virtuoso RF Solution , Virtuoso RF , Layout EXL , Chinese blogs

Breakfast Bytes

Sunday Brunch Video for 8th August 2021

https://youtu.be/_dRTQm0DyG0 Made in New York City (camera Carey Guo) Monday: Intel…

• less than a min read
sunday brunch

Computational Fluid Dynamics

This Week in CFD

Welcome to the weekend. It's time for This Week in CFD , all the CFD news that I…

• less than a min read
CFD , Computational Fluid Dynamics , fluid dynamics , CFD Applications

カスタムIC／ミックスシグナル

Virtuosity: 分散型ファームにおけるリソースの最適な利用

読者の皆さん、こんにちは。 ジョブやシミュレーションを実行するために、どれくらいのリソースが必要なのか、誰しも疑問に思ったことがありますよね。これは難しい問題で…

• less than a min read
SGE , Analog Design Environment , LBS , Job Policy , ADE , LSF , Virtuoso , Virtuosity , distributed processing , japanese blog , Custom IC Design , IC6.1.8 , Assembler , ADE Assembler

Breakfast Bytes

Offtopic: Today You, Tomorrow Me

It is the last day before a break and so I write about whatever I feel like. It's…

• 7 min read
offtopic

System, PCB, & Package Design 

ASCENT: More Reasons to Move to 17.4-2019 Hotfix 019

Picking up from where we left off in the previous post , let’s look at some more…

• 4 min read
System Capture , 17.4 , publish for manufacturing , LIVE BOM , 17.4-2019 , Allegro Pulse , hotfix 019 , Allegro System Capture , PLM , web dashboard , ASCENT , Allegro

Breakfast Bytes

The Systems Designer's Guide to...Systems Analysis

There is a new book in the System Designer's Guide to... series, published by i.007e…

• 5 min read
featured post , system analysis , electrical analysis , Thermal Analysis

Breakfast Bytes

Intel's Process and Packaging Roadmaps

There are only three companies that are on the real leading edge. As you probably…

• 5 min read
Intel , intel 4 , featured post , intel 7 , emib , process roadmap , intel 3 , foveros , intel 20a

Breakfast Bytes

Sunday Brunch Video for 1st August 2021

https://youtu.be/I0AYf5V_irg Made in Long Ridge Open Space Preserve (camera Carey…

• less than a min read
sunday brunch

Computational Fluid Dynamics

This Week in CFD

It's a Global Recharge Day here at Cadence so why not get recharged by keeping up…

• 1 min read
CFD , Automotive , Computational Fluid Dynamics , CFD Vision 2030 , CFD Applications

Analog/Custom Design

Spectre Tech Tips: Spectre High Impedance Node Check Overview

Circuit checks enable you to analyze typical design problems, such as high impedance…

• 4 min read
spectre aps , dyn_floatdcpath , dyn_float_tran_stat , dyn_highz , highz , static_highz , Spectre , static checks , spectre x , Design Checks , floating node

System, PCB, & Package Design 

System Analysis Knowledge Bytes: Computational Fluid Dynamics Roundup – July 202…

Welcome to the Computational Fluid Dynamics Roundup series, your monthly roundup…

• 5 min read
CFD , System Analysis Knowledge Bytes , Pointwise , Computational Fluid Dynamics , NUMECA , Mesh Generation , Meshing , Omnis

System, PCB, & Package Design 

ASCENT: Reasons to Move to 17.4-2019 Hotfix 019

“The only constant in life is change” nowhere is this adage truer than in the world…

• 4 min read
17.4 , DRC , logical design , Layout , 17.4-2019 , audit , Allegro System Capture , ASCENT , Schematic , Allegro

System, PCB, & Package Design 

IC Packagers: Reuse Wirebond Placement with Place Replicate Modules

Most package designs have wire bonding and reusing the wire bond information for…

• 3 min read
17.4 QIR3 , 17.4 , APD , IC Packaging & SiP design , Allegro Package Designer , 17.4-2019 , ICPackagers
CDNS - Fix Layout Hompage