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Corporate News

Honda + Cadence = Physical AI (part 3): Creating a Chip the World Has Never Seen

Hello everyone. I'm Kentaro Komori, an engineer in the Semiconductor Research at…

Corporate
• 9 min read
featured , physical ai , HGR , AI , Honda

Corporate News

See AuraStack AI Super Agent in Action!

Modern AI systems are pushing electronic design into a new phase of complexity. High…

Reela Samuel
• 3 min read
AuraStack AI Super Agent , Allegro X AI , featured , agentic ai , Super Agent

Corporate News

DAC 2026 Wrap-Up: AI-Powered Engineering Moves from Vision to Workflow Reality

Every year, Design Automation Conference (DAC) brings big announcements, packed demos…

Corporate
• 5 min read
Jasper Formal Verification Platform , featured , agentic ai , DAC 2026 , AI for design

Corporate News

Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution

Today, AI infrastructure is driving a fundamental shift in semiconductor design.…

Corporate
• 7 min read
featured , chiplets , infrastructure ai , SF2P , physical ai
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Blog - Post List
Latest blogs

Corporate News

Jilin University Accelerates Student Racing Success Using Fidelity CFD Software

Founded in 1955, the College of Automotive Engineering at Jilin University has a…

• 2 min read
CFD , designed with cadence , Fidelity CFD

Physical Systems Simulation (CAE)

The Sound of Silence as AI Rewrites EV NVH Engineering

Step into a modern electric vehicle, and one thing becomes immediately clear: the…

• 6 min read
MSC Nastran , electric vehicles , Actran , NVH simulation , simulation software , ODYSSEE

Digital Design

Accelerate Design Signoff with the Updated Cadence Voltus Training Kit

By Ronen Stilkol, Senior AE Architect As advanced-node and 3D-IC designs push higher…

• 8 min read
package , Voltus , die , VTK

Learning and Support

Cadence Welcomes Xinqiao Electronics to the Certified Training Partner Program

The semiconductor industry requires a highly skilled workforce and demands that recent…

• 1 min read
PCB , Cadence training , bridgingthelearninggap , PCB design , Cadence Education Services , learning and support , Training Partners

Verification

PSS 3.1 Channels: The Game Changer for Target-Time Communication

Portable Stimulus models already feature powerful language constructs to describe…

• 7 min read
PSS 3.1 , Perspec , System Design and Verification , channels , perspec system verifier , target time communication

Analog/Custom Design

Smart Corners Analysis Helps You Focus on the Conditions That Matter the Most!

Imagine you are designing a precision analog block targeted for a high‑volume product…

• 5 min read
blended training , Corners , Cadence blogs , Spectre FMC Analysis , Virtuoso Studio , Spectre FMC , analog , Fast Monte Carlo Analysis , worst case corners , Monte Carlo analysis , Virtuoso Analog Design Environment , digital badges , training bytes , Virtuoso , ADE Artist , Custom IC Design , Custom IC , Cadence Community

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

• 6 min read
infrastructure ai , agentic ai , physical ai , sciences ai , Three-Layer Cake , AI-Driven Design , AI for design , design for AI

Corporate News

The Three-Layer Cake: The Foundation Behind Intelligent Engineering

Artificial intelligence is rapidly becoming the engine behind the next era of technology…

• 7 min read
infrastructure ai , agentic ai , Principled Simulation , physical ai , Three-Layer Cake , AI-Driven Design , AI for design , Agents , design for AI , AI

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

• 6 min read
Allegro X AI , infrastructure ai , agentic ai , Integrity 3D-IC Platform , physical ai , Semiconductor Innovation , AI for design , ChipStack AI Super Agent , design for AI , Clarity 3D Solver , Super Agents

Corporate News

AI Infrastructure Starts Beyond the Chip

Why Advanced Packaging and PCB Design Have Become the Next Frontier of Innovation…

• 8 min read
chip , featured , AI infrastructure , agentic ai , packaging , physical ai , Super Agent , AuraStack , AI for design , PCB design , AI , multiphysics

Physical Systems Simulation (CAE)

The Top Five Reasons to Use Cradle CFD 2026.1

If you’ve been weighing whether it’s time to upgrade your CFD software , Cradle CFD…

• 2 min read
CFD , MSC Software , Cradle CFD

Digital Design

Cadence RTL Design Studio: Built for the Full PPAC Journey

If you've used Joules RTL Design Studio, you already know what it can do. Now it…

• 2 min read
Digital Design and Signoff , featured , Joules , Digital Implementation , rtlstudio , front end design , Joules RTL Design Studio

Digital Design

The Truth About Complete DFT Flow: What Most Engineers Miss

Design for Testability is a critical step in achieving high-quality silicon. In this…

• 4 min read
DFT , Genus , Modus DFT , Fault Diagnostics , Logic Design , training bytes , Genus Synthesis Solution , ATPG , Synthesis , Modus ATPG

Verification

Why 10BASE-T1S Automotive Ethernet SoC Verification Needs More Than Simulation?

Cadence Multi-Platform Verification improves functional coverage and verification…

• 5 min read
Verification IP , Emulation , simulation

Computational Fluid Dynamics

How Fidelity CFD Improves Hydraulic Turbine Performance Prediction

Francis-99 Hydraulic Turbine (Trivedi, 2026) Accurately predicting the performance…

• 5 min read
Fidelity Charles Solver , CFD , turbomachinery , Hydraulic Turbines , Fidelity Turbo , Francis Turbine

Corporate News

How the New ASK AI Assistant Makes Support More Seamless

Finding the right answer often takes more than one question. Users may start with…

• 2 min read
featured , customer support , Generative AI , ASK Portal , ASK AI Assitant

Artificial Intelligence (AI)

You'll Still Do the Work—You Just Won't Do the Boring Part

Agentic AI is about to change your flow. Here's what actually shifts—and why the…

• 5 min read
artificial intelligence , featured , agentic ai , NVIDIA , AI for design

Verification

Understanding PCIe 6.0 Power States: L0p vs L0s vs L1

PCI Express has always focused on a single goal: maximizing performance while minimizing…

• 5 min read
Verification IP , PCIExpress , PCIe 6.0

Corporate News

How Cadence and TSMC Are Accelerating AI Silicon Design at Advanced Nodes

Designing AI silicon for increasing AI/HPC workloads at advanced nodes has become…

• 5 min read
Advanced Node , TSMC Certified design flows , AI silicon
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