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Physical Systems Simulation (CAE)

Everything to Look Forward to in Actran 2026.1

Cadence has released Actran 2026.1 , and this version adds more capabilities to two…

Cadence MSC Software 10 Jul 2026 • 2 min read

Actran , Acoustic Simulation , PSDA , simulation software , NVH , FEA , CAE Software

System, PCB, & Package Design

High-Speed Heterogeneous Integration with Multiphysics Analysis for TSMC SoW-X

2.5D advanced packaging is becoming increasingly critical as the demand for AI and…

MSATeam 7 Jul 2026 • 2 min read

ucie , Sigrity X , SoW-X , Advanced IC packaging , Power Integrity , Signal Integrity , Clarity 3D Solver , PowerSI , multiphysics

Verification

From Pacemakers to ADAS: Verifying Systems Before Tapeout

Imagine discovering a critical bug in a heart pacemaker, not after deployment, not…

Reela Samuel 7 Jul 2026 • 6 min read

Automotive , Protium , Palladium , medical , robotics , verification

Verification

DFI 6.0 Key Highlights of the Latest DFI Specification

The DDR PHY Interface (DFI) protocol specifies the signals, timing parameters, and…

Shyam Sharma 7 Jul 2026 • 4 min read

Verification IP , memory controller , PHY , VIP , hbm4 , DFI , DRAM , DFI 5.2 , DFI 6.0 , memory models , Lpddr6

Computational Fluid Dynamics

Fidelity Fine Marine for Faster, Smarter Marine Design Decisions

Marine design engineers and naval architects increasingly rely on computational fluid…

Veena Parthan 7 Jul 2026 • 5 min read

CFD , marine applications , FINE Marine , Fidelity CFD , simulation software

Verification

UALink Under the Hood: Why Full-Stack Verification Wins

Inside the UALink stack: How 640 bytes travel from intent to wire, and why full-stack…

Sandeep Grover 5 Jul 2026 • 5 min read

Verification IP , UAL , verification strategy , System Design and Verification , VIP , UALink , verification

Cloud

When Infrastructure Becomes the Bottleneck in Chip Design

How Cadence OnCloud Managed Service Is Rewriting the Rules for Chip Design As chip…

Vinod Khera 5 Jul 2026 • 7 min read

Cadence Managed Cloud , OnCloud Marketplace , cadence cloud , cloud eda

Digital Design

Boost Design Productivity by Cadence Digital Tools: Webinar Recording Available!

This webinar series delivers practical methodologies and tool insights to help digital…

sakshin 1 Jul 2026 • 2 min read

Cadence Online Support , webinar , Digital Implementation

Verification

NVMe 2.0 Explained: What’s New and Why It Matters

Non-Volatile Memory Express (NVMe) has become the dominant protocol for high-performance…

Vishal Patel 1 Jul 2026 • 5 min read

NVMe 2.0 , Verification IP , non-volatile memory , NVM Express , NVMe , Non-Volatile Memory Express , VIP , Zoned Namespaces , NVMe Verification IP , NVMe specification , ZNS

System, PCB, & Package Design

BoardSurfers: Installation Know-How: Cadence Licensing Floating vs. Single User

In PCB design teams today, the way licenses are managed can have a direct impact…

Shikha Jain 1 Jul 2026 • 3 min read

OrCAD X Capture , Installation Know-How , cadence , license , SUL , PCB design , OrCAD X Presto , OrCAD X , installation , OrCAD X PCB Layout

Digital Design

Mastering Advanced Debug in Conformal LEC: Mapping to AI Driven Abort Resolution

This blogs provides a structured learning approach to Conformal LEC debug that combines…

sakshin 30 Jun 2026 • 2 min read

conformal lec , Equivalence Checking , cadence learning and support

Verification

Understanding USB4 Retimers and Their Role in Gen2 and Gen3 - Link Training

USB4 systems rely on retimers to enable reliable high-speed communication across…

SS202605248717 30 Jun 2026 • 5 min read

USB4 VIP , usb4 , retimers

Artificial Intelligence (AI)

The Feedback Loop Is the Moat

Every verification and design team I talk to is building agents right now. The demos…

Hamid Shojaei 30 Jun 2026 • 14 min read

featured , AI in chip design , GenAI , AI/ML

Digital Design

Smarter DFT Starts at RTL: A Deep Dive into Modern DFT Flows with Genus

This blog showcases the benefits of integrating DFT features within the synthesis…

sakshin 30 Jun 2026 • 1 min read

DFT , webinar , implementation , Genus Synthesis Solution , cadence learning and support

Verification

The Infineon Automotive Ecosystem Summit 2026

The 2026 Infineon Automotive Ecosystem Summit took place in late June at the Infineon…

JEngblom 30 Jun 2026 • 2 min read

Automotive , Infineon , vlab , Digital Twins

Life at Cadence

Cadence Giving Foundation Leads a Day of Collective Community Impact

On June 25, the Cadence Giving Foundation brought together an extraordinary coalition…

Corporate 30 Jun 2026 • 2 min read

Cadence Giving Foundation , featured , san jose , Collective Impact Day , City Year Bay Area , life at cadence

Life at Cadence

Finding Our Voice Together with Toastmasters

At Cadence, innovation begins with people. While breakthrough technologies, industry…

Reela Samuel 30 Jun 2026 • 3 min read

Toastmasters , great place to work , life at cadence , One Cadence One Team

Digital Design

RTL Design Studio: Bridging RTL Design and Physical Implementation

The blog introduces RTL Design Studio as a breakthrough solution that empowers engineers…

sakshin 26 Jun 2026 • 2 min read

Digital Implementation , RTL design , RTL debugging , physical implementation , LMS , Joules RTL Design Studio , cadence learning and support

Digital Design

Low-Power Equivalence Checking in Modern SoC Flows

Background: Why Low-Power Equivalence Checking? In modern SoC design, advanced…

Atreya 26 Jun 2026 • 5 min read

Low Power , Silicon Signoff and Verification , Digital Implementation

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