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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Analog/Custom Design

Liberate Trio: A Scalable Answer to Advanced-Node Characterization

The Growing Pain No Library Team Can Ignore If you're working on standard-cell…

• 4 min read
nldm , AdvancedNodes , HighPerformanceComputing , MultiPVT , library characterization , recharacterization , ChipDesignTraining , bolt , Recovery characterization , CadenceLiberate , LiberateTrio , Debugging Techniques in Liberate Trio , VLSItraining , Liberate , MPVT characterization , Liberty , StandardCellLibraries , ParallelProcessing , ECSM , CCS , liberty model , Model Files , EDAlearning

Verification

Cadence Announces PCIe 8.0 Verification IP Availability at PCI‑SIG US

At the recent  PCI ‑ SIG Developers Conference US held on May 6-7,2026 , Cadence…

• 2 min read
Verification IP , Functional Verification , pcie 8.0

Analog/Custom Design

Virtuoso Studio: Excellent XL – Automated Layout XL Binding from LVS Data

Click here to discover how Virtuoso Studio IC25.1 uses LVS svdb data for automated…

• 2 min read
Virtuoso Layout Suite MXL , arc , svdb , Layout Xl Binding , LVS-based Binding , Application Readiness Checker , Virtuoso Layout Suite XL

カスタムIC／ミックスシグナル

Virtuoso Studio: Layout Editorにおける生産性の向上--ブログシリーズ

カスタムICレイアウトという複雑な世界において、マウスのクリックやキーボードのキーの一つ一つが、生産性に大きな影響を及ぼします。この点を踏まえ、Virtuoso…

• less than a min read
Virtuoso Studio , japanese blog , Custom IC Design

SoC and IP

Beyond PCIe Compliance: Why Stress Testing Is Crucial for Edge AI Deployments

Passing PCI Express (PCIe) compliance is different from being ready for the field…

• 4 min read
Edge AI , Design IP , validation , PHY , Edge Computing , compliance , stress testing , PCIe , SerDes IP

System, PCB, & Package Design 

Machine Learning Models for SI/PI Analysis with Meshed Planes

As data rates continue to scale into the multi-tens of gigabits per second, the tolerance…

• 2 min read
3D-IC , Power Integrity , IC Packaging & SiP design , machine learning , Signal Integrity , PCB design , Clarity 3D Solver

SoC and IP

Cadence Demonstrates PCIe 8.0 PHY at PCI-SIG DevCon 2026

The accelerated growth in data processing and storage demands across HPC data centers…

• 2 min read
AI data center , data center , hyperscale data center , AI factory

SoC and IP

Securing Scale-Up AI: Cadence’s Complete UALink Solution

As AI systems continue to scale, adding more compute is no longer the biggest challenge…

• 4 min read
security , IP , UALink , UALinkSec , datacenter , AI

Corporate News

ams OSRAM: Lighting the Path Forward with Intelligent Sensing

For more than a century, ams OSRAM has stood at the forefront of light and sensor…

• 2 min read
designed with cadence

Analog/Custom Design

Analog Circuit Modeling Using Verilog-A within Virtuoso: A Video Series

A Practical Video Series that connects Verilog‑A Modeling to Real Circuit Behavior…

• 6 min read
Cadence blogs , ADE Explorer , Virtuoso Analog Design Environment , analog behavioral models , training bytes , Virtuoso , Spectre , Custom IC Design , Verilog-A

Verification

VLAB at the MATLAB Expo Japan 2026

The Cadence VLAB team will be part of the Cadence team present at the MATLAB Expo…

• 1 min read
Automotive , Simulink , vlab , MBSE , Testing , event , verification , Matlab

SoC and IP

PCIe 7.0 for AI Factories: Why Bandwidth Alone Isn’t Enough

AI factories are scaling rapidly. Training large models and delivering low‑latency…

• 1 min read
Design IP , AI data center , AI Inferencing , DIP , AI Factories , PCIe 7.0 , PCIe , AI training , PCIe 6.0

Corporate News

2.5D + 3D = “3.5D”!

Architecting the Next Generation of AI Silicon The semiconductor industry is no longer…

• 5 min read
Allegro X AI , Integrity 3D-IC Platform , 3D-IC , advanced packaging , AI-Driven Design , AI for design , 3.5D , AI/ML , AI , 2.5D , semiconductors

Computational Fluid Dynamics

Structured or Unstructured Meshes: What Works Best for Turbomachinery CFD

In computational fluid dynamics (CFD), meshing is a critical step for achieving reliable…

• 2 min read
Fidelity Hexpress , GAMM Turbine , Fidelity Autogrid , turbomachinery , S2V meshing , Computational Fluid Dynamics , structured meshing , unstructured meshing , Meshing , Fidelity Flow

Analog/Custom Design

Legacy Node to Advanced Silicon: Schematic Migration in Cadence Virtuoso Studio

In today’s fast-paced semiconductor industry, technology nodes evolve quickly—yet…

• 3 min read
Virtuoso Studio , Cadence training , Custom IC Design

Verification

Unraveling Precision Time Measurement (PTM)

Introduction Precision Time Measurement (PTM) is an optional capability for communicating…

• 5 min read
Verification IP , PCIe 6.0

カスタムIC／ミックスシグナル

初期検討から最終最適化までのRF設計の高速化

村田製作所は、Virtuoso Studio RF向けチューニングおよび最適化ライブラリをリリースしました。 RFおよびマイクロ波システムは、5G/6G、自動車レーダー…

• less than a min read
RF Simulation , analog/RF , awr , Virtuoso RF , RF design , microwave office , japanese blog

Analog/Custom Design

New Spectre AMS Designer Features in XCELIUM 26.03

The Spectre AMS Designer features are now available through the XCELIUM 26.03 release…

• 1 min read
AMS-Designer , AMSD , Spectre AMS Designer , AMSD Simulation , AMS-X GPU , analog assertions , idspf

System, PCB, & Package Design 

Mastering Library Development in Allegro X System Capture

Modern schematic-driven design flows rely on accurate, reusable, and well-structured…

• 2 min read
System Capture , SPB , Allegro
CDNS - Fix Layout Hompage