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Featured

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
Corporate 2 Oct 2025 • 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
Corporate 1 Oct 2025 • 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
Vinod Khera 28 Sep 2025 • 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
Virtuoso Release Team 25 Sep 2025 • 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso
cdns - all_blogs_categories

  • All 6077
  • Corporate News 201
  • Life at Cadence 200
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  • Analog/Custom Design 765
  • Artificial Intelligence 23
  • Cloud 16
  • Computational Fluid Dynamics 361
  • Data Center 39
  • Digital Design 427
  • Learning and Support 55
  • RF Engineering 114
  • SoC and IP 413
  • System, PCB, & Package Design  986
  • Verification 1286
  • Cadence Japan 3

  • CFD(数値流体力学) 45
  • 中文技术专区 15
  • カスタムIC/ミックスシグナル 188
  • PCB、IC封装:设计与仿真分析 136
  • PCB解析/ICパッケージ解析 44
  • PCB設計/ICパッケージ設計 61
  • RF /マイクロ波設計 44
  • Spotlight Taiwan 61
  • The India Circuit 89
  • 定制IC芯片设计 79
  • データセンター 7

  • Whiteboard Wednesdays 253
Blog - Post List

Latest blogs

SoC and IP

TWS Earbud Design Is About Scaling

It is important that OEMs and SoC providers of TWS earbuds prepare to offer the quality…

The Prakashian 4 Apr 2022 • 5 min read
featured , Tensilica

Verification

LPDDR5 Verification from PHY to System Level

LPDDR5 DRAM aims to serve a wide array of markets and plays a vital role in the system…

Vinod Khera 4 Apr 2022 • 6 min read

Breakfast Bytes

Intelligent System Analog Design

There are many perceptions about analog design that might have been true once. For…

Paul McLellan 4 Apr 2022 • 6 min read
analog , Virtuoso , mixed signal , Virtuoso Layout Suite EXL

PCB設計/ICパッケージ設計

BoardSurfers: Allegro PCB Editorでの寸法データ入力に関する概要

プリント基板がより複雑かつ軽量になっていく中、費用対効果が高く信頼性の高い基板の設計・製造は、これまで以上に重要となっています。デザインの詳細情報が不正確/不完全では…

SPB Japan 3 Apr 2022 • less than a min read
17.4 , BoardSurfers , manufacturing , japanese blog , Allegro PCB Editor , Allegro

Computational Fluid Dynamics

Combining Structured and Unstructured Meshes: The Holy Grail for CFD Engineers

Flow solvers must be able to read the type of meshes behind them, and as most flow…

AnneMarie CFD 1 Apr 2022 • 4 min read
CFD , Automated meshing , mesh , structured grids , Computational Fluid Dynamics , fluid dynamics , structured meshing , CFD Applications , unstructured meshing , simulation software , Meshing , simulation , unstructured grids

Breakfast Bytes

The All-Purpose EDA Keynote

Today, it is April 1st and so it is tempting to do some spoof post, but most of those…

Paul McLellan 1 Apr 2022 • 5 min read
edagraffiti , Blogging , parody , keynote

Life at Cadence

Celebrating Women's History Month with Girl Geek X!

To celebrate Women’s History Month in March, Cadence partnered with Girl Geek X for…

Mary Kasik 31 Mar 2022 • 1 min read
inclusion , Women at Cadence , women , Women's History Month , girl geek , diversity , Women in Technology

Breakfast Bytes

DVCon: There Be Dragons!

At the recent DVCon, there was a panel session titled SoC Verification Hidden Dragons…

Paul McLellan 31 Mar 2022 • 12 min read
formal , Emulation , DVcon , simulation , verification

System, PCB, & Package Design 

Cadence OrCAD and Allegro 17.4-2019 HotFix SPB17.40.028 is Now Available

The HotFix 028 (QIR4, indicated as 2022 in the application splash screens) update…

AllegroReleaseTeam 31 Mar 2022 • 6 min read
Cadence Design Systems , 17.4 , PSpiceA/D , PSPICE , PCB Editor , 17.4-2019 , OrCAD , PCB design , Allegro System Capture , Pulse , Allegro

Analog/Custom Design

Spectre Tech Tips: Using DSPF Post-Layout Netlists in Spectre Circuit Simulator

DSPF files are an integral part of post-layout simulations. This blog introduces…

Stefan Wuensche 31 Mar 2022 • 5 min read
spectre aps , post-layout simulation , EMIR Analysis , EMIR Simulation , DSPF , netlist , Spectre , Spectre X Simulator , EMIR

CFD(数値流体力学)

Illinois Blowerは流体シミュレーションによってファンの性能を44%改善

石油化学およびその他の産業では、空気の換気や500°C以上の有害な塩化物ガスの処理のためにファンを使用しています。これらのファンの最大運転回転速度は業界標準によって管理され…

CFD Japan 30 Mar 2022 • less than a min read
CFD , turbomachinery , fans , Computational Fluid Dynamics , fluid dynamics , simulation software , japanese blog , simulation

Computational Fluid Dynamics

Shortage of Chips a Challenge for Vehicle Electrification

Electric Vehicle (EV) market growth, along with the bourgeoning investments in autonomous…

Veena Parthan 30 Mar 2022 • 5 min read
battery capacity , Automotive , gallium nitride , electric vehicles , intelligent manufacturing , chip production , Silicon chips , silicon carbide

Computational Fluid Dynamics

Illinois Blower Increases Fan Performance by 44% with Fluid Dynamics Simulation

Illinois Blower develops and builds custom centrifugal fans and blowers for a variety…

AnneMarie CFD 30 Mar 2022 • 5 min read
CFD , turbomachinery , fans , Computational Fluid Dynamics , fluid dynamics , simulation software , simulation

Analog/Custom Design

Virtuoso ICADVM20.1 ISR24 and IC6.1.8 ISR24 Now Available

The ICADVM20.1 ISR24 and IC6.1.8 ISR24 production releases are now available for…

Virtuoso Release Team 30 Mar 2022 • 2 min read
Analog Design Environment , Cadence blogs , Virtuoso RF Solution , IC Release Announcement blog , Virtuoso Visualization and Analysis XL , Virtuoso RF , Layout EXL , Virtuoso Analog Design Environment , Virtuoso , ICADVM20.1 , IC Release Blog , Virtuoso ADE Explorer , Virtuoso Layout Suite , Custom IC , Virtuoso ADE Assembler , IC6.1.8

Breakfast Bytes

ESD Alliance CEO Outlook (and the Kaufman Dinner)

The ESD Alliance has two events coming up in the next couple of months, both of which…

Paul McLellan 30 Mar 2022 • 2 min read
kaufman dinner , semi , ceo outlook , esd alliance

カスタムIC/ミックスシグナル

Virtuoso Meets Maxwell: RF回路でのカスタム受動デバイス – デバイスかそれともインターコネクトか

'Virtuoso Meets Maxwell' はVirtuoso RF ソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

Custom IC Japan 29 Mar 2022 • less than a min read
S-parameter , Extraction , Smart View , Layout versus schematic , pegusas , RFIC , parasitic , LVS , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Electromagnetic Solver , Electromagnetic analysis , EMX , Quantus Extraction Solution , graybox , ICADVM20.1 , japanese blog , blackbox , Quantus , Custom IC Design , EMX Solver , VMM

Computational Fluid Dynamics

CFD Wind Studies for Ship Superstructures

Besides resistance, seakeeping and propulsion, wind loads play an important role…

AnneMarie CFD 29 Mar 2022 • 2 min read
CFD , naval archicture , Marine Engineering , shipping , marine , fine/marine , Wind Study , Computational Fluid Dynamics , fluid dynamics , IMO regulations , CFD Applications , simulation software , NUMECA , naval

Breakfast Bytes

The Framework Laptop and Right to Repair

You might have heard some discussion about "the right to repair" or R2R. Some of…

Paul McLellan 29 Mar 2022 • 5 min read
framework laptop , right to repair , r2r

Verification

How to Verify JEDEC DRAM Memory Controller, PHY, or Memory Device?

DDR Memory is an important part of a wide array of electronic system designs in various…

ssalehab 29 Mar 2022 • 2 min read
Verification IP , Industry Insights , Functional Verification , DFI 5.1 , VIP , SoC , DFI , storage , DFI Technical Group , memory models , DDR-PHY , DDR-PHY Interface
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