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The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
• 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA

Corporate News

Honda + Cadence = Physical AI (part 2): Where Physical AI Will Be Won

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The real challenge of physical…

Corporate
• 8 min read
featured , physical ai , HGR , AI , Honda
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Blog - Post List
Latest blogs

Digital Design

Unlocking PPA with Innovus: What’s New and How to Unleash It

Design teams building low-power silicon face nonstop PPA pressure: reduce dynamic…

• 7 min read
Digital Implementation , Innovus

Analog/Custom Design

Electrically Aware Design: Catch EM and IR Drop Issues Early with EAD

As designs move to advanced nodes, interconnect reliability is pushed to its limits…

• 5 min read
EAD , electromigration , Cadence blogs , Virtuoso Studio , electrically-aware design flow , Simulation-driven interactive routing , LDE , digital badges , Custom IC Design , SDR , ADE Assembler

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO , ITF World 2026 , CEFT , design for AI

カスタムIC／ミックスシグナル

Virtuoso Studio: Layout Editorにおける生産性の向上--ブログシリーズ1

本ブログでは、Group Arrayの機能強化にフォーカスしています。Group Arrayはレイアウトの生産性において極めて重要な要素であり、設計者はこれを用いることで…

• less than a min read
Virtuoso Studio , japanese blog , Custom IC Design , Virtuoso Layout Suite XL

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis

RF Engineering

Agentic AI for RF Design: A Practical Path to Faster Execution

How Cadence AI supports greater engineering productivity In RF design, the most useful…

• 3 min read
agentic ai , Virtuoso RF , RF design

Data Center

Cadence and Microsoft Present New Insights on Data Center CFD Modeling at ITherm

As AI workloads continue to drive unprecedented rack power densities, the limits…

• 2 min read
CFD , data center , data center cooling , digital twin

Physical Systems Simulation (CAE)

Fewer FEA Frustrations: A Smarter Way to Debug MSC Nastran Models

If you've spent hours hunting down a mysterious solver error or scratching your head…

• 2 min read
MSC Nastran , PSDA , SDA , CAE Software

System, PCB, & Package Design 

Ascent: Training Insights: PCB Design Flow in Allegro X PCB System Capture

Designing modern PCBs requires speed, accuracy, and a seamless transition from concept…

• 5 min read
Allegro X PCB Editor , Allegro X layout editors , PCB design , allegro x , Allegro X System Capture

Analog/Custom Design

Liberate Trio: A Scalable Answer to Advanced-Node Characterization

The Growing Pain No Library Team Can Ignore If you're working on standard-cell…

• 4 min read
nldm , AdvancedNodes , HighPerformanceComputing , MultiPVT , library characterization , recharacterization , ChipDesignTraining , bolt , Recovery characterization , CadenceLiberate , LiberateTrio , Debugging Techniques in Liberate Trio , VLSItraining , Liberate , MPVT characterization , Liberty , StandardCellLibraries , ParallelProcessing , ECSM , CCS , liberty model , Model Files , EDAlearning

Verification

Cadence Announces PCIe 8.0 Verification IP Availability at PCI‑SIG US

At the recent  PCI ‑ SIG Developers Conference US held on May 6-7,2026 , Cadence…

• 2 min read
Verification IP , Functional Verification , pcie 8.0

Analog/Custom Design

Virtuoso Studio: Excellent XL – Automated Layout XL Binding from LVS Data

Click here to discover how Virtuoso Studio IC25.1 uses LVS svdb data for automated…

• 2 min read
Virtuoso Layout Suite MXL , arc , svdb , Layout Xl Binding , LVS-based Binding , Application Readiness Checker , Virtuoso Layout Suite XL

カスタムIC／ミックスシグナル

Virtuoso Studio: Layout Editorにおける生産性の向上--ブログシリーズ

カスタムICレイアウトという複雑な世界において、マウスのクリックやキーボードのキーの一つ一つが、生産性に大きな影響を及ぼします。この点を踏まえ、Virtuoso…

• less than a min read
Virtuoso Studio , japanese blog , Custom IC Design

SoC and IP

Beyond PCIe Compliance: Why Stress Testing Is Crucial for Edge AI Deployments

Passing PCI Express (PCIe) compliance is different from being ready for the field…

• 4 min read
Edge AI , Design IP , validation , PHY , Edge Computing , compliance , stress testing , PCIe , SerDes IP

System, PCB, & Package Design 

Machine Learning Models for SI/PI Analysis with Meshed Planes

As data rates continue to scale into the multi-tens of gigabits per second, the tolerance…

• 2 min read
3D-IC , Power Integrity , IC Packaging & SiP design , machine learning , Signal Integrity , PCB design , Clarity 3D Solver

SoC and IP

Cadence Demonstrates PCIe 8.0 PHY at PCI-SIG DevCon 2026

The accelerated growth in data processing and storage demands across HPC data centers…

• 2 min read
AI data center , data center , hyperscale data center , AI factory

SoC and IP

Securing Scale-Up AI: Cadence’s Complete UALink Solution

As AI systems continue to scale, adding more compute is no longer the biggest challenge…

• 4 min read
security , IP , UALink , UALinkSec , datacenter , AI

Corporate News

ams OSRAM: Lighting the Path Forward with Intelligent Sensing

For more than a century, ams OSRAM has stood at the forefront of light and sensor…

• 2 min read
designed with cadence

Analog/Custom Design

Analog Circuit Modeling Using Verilog-A within Virtuoso: A Video Series

A Practical Video Series that connects Verilog‑A Modeling to Real Circuit Behavior…

• 6 min read
Cadence blogs , ADE Explorer , Virtuoso Analog Design Environment , analog behavioral models , training bytes , Virtuoso , Spectre , Custom IC Design , Verilog-A
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