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Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent

Corporate News

AI Infrastructure Starts Beyond the Chip

Why Advanced Packaging and PCB Design Have Become the Next Frontier of Innovation…

Corporate
• 8 min read
chip , featured , AI infrastructure , agentic ai , packaging

Digital Design

Cadence RTL Design Studio: Built for the Full PPAC Journey

If you've used Joules RTL Design Studio, you already know what it can do. Now it…

raquelp
• 2 min read
Digital Design and Signoff , featured , Joules , Digital Implementation , rtlstudio

Corporate News

How the New ASK AI Assistant Makes Support More Seamless

Finding the right answer often takes more than one question. Users may start with…

Corporate
• 2 min read
featured , customer support , Generative AI , ASK Portal , ASK AI Assitant
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Blog - Post List
Latest blogs

Analog/Custom Design

Design Smart, Sign Off Smarter: Voltus-XFi for Transistor-Level Power Signoff

Imagine you've just built your dream home. You’ve double-checked the plumbing, inspected…

• 5 min read
Analog Design Environment , Cadence blogs , Virtuoso Studio , custom/analog , ADE Explorer , Routing , Virtuoso Layout EXL , analog , Virtuoso Visualization and Analysis XL , training , Layout Suite , Virtuoso Analog Design Environment , digital badges , training bytes , Layout , Virtuoso , Spectre , Cadence certified , Analog Design Environment , ViVA , Virtuosity , cadenceblogs , Virtuoso Video Diary , Circuit Design , Cadence Education Services , analog design , spectre x , Custom IC Design , online training , Virtuoso Layout Suite , Custom IC , Cadence Community , Assembler , Spectre X Simulator , ADE Assembler , IC23.1

System, PCB, & Package Design 

Training Insights: Migrating from Allegro DE-HDL to Allegro X System Capture

Explore the strategic and technical benefits of transitioning to Allegro X System…

• 2 min read
PCB , webinar , Design Entry HDL , PCB design , allegro x , Allegro , Allegro X System Capture

Learning and Support

GenAI-Powered ASK AI Assistant Now Live on Cadence ASK Portal

You might remember the blog about the GenAI Feature on Cadence ASK that we published…

• 1 min read

System, PCB, & Package Design 

PCB Design Workflow Using Sigrity X for Signal and Power Integrity Analysis

Jasmine Vital Muniz, Electrical Engineer, OLogic, Inc. While many electronic design…

• 1 min read
PCB , SIPI , Sigrity X , Power Integrity , SI/PI Analysis , Signal Integrity

SoC and IP

Redefining SoC Design: The Shift to Secure Chiplet-Based Architectures

The semiconductor industry is undergoing a paradigm shift from monolithic system…

• 5 min read
security , Automotive , chiplets , physical ai , SoC

Corporate News

Cadence Launches Cache-Coherent HiFi 5s SMP for Next-Gen Audio Applications

Next-generation consumer and automotive audio is becoming increasingly sophisticated…

• 4 min read
news story , featured , Symmetric Multiprocessing , audio , Silicon Solutions , HiFi , Front Page Press Release , SMP , Tensilica , SSG , Xtensa

Verification

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium , Palladium , xcelium , VDE , helium , System Verification

RF Engineering

Empowering RF Power: Must-See Video Series for AWR Users!

Calling all AWR Microwave and RF designers—getting the most out of your tools just…

• 1 min read
RF , RF Simulation , analog/RF , Cadence Academic Network , AWR Design Environment , Virtuoso RF , Electromagnetic analysis , Analyst 3D FEM EM Simulator , RF design , AWR Microwave Office , AXIEM 3D Planar Simulator , microwave office , Visual System Simulator (VSS)

System, PCB, & Package Design 

Cadence Customers Share Experiences with Revolutionary PCB Design Methodology

PCB design teams are often caught in a repetitive cycle of design and simulation…

• 3 min read
Automotive , si/pi , Sigrity X Aurora , MIPI , PCB design , ADAS , allegro x

Academic Network

Accelerating Innovation: The SolarCar at Virginia Tech Team

At a time when sustainability and innovation are beautifully coming together, the…

• 2 min read
featured , Cadence Academic Network , CFD Simulations , Solar Car

SoC and IP

Cadence Leads the Way at PCI-SIG DevCon 2025 with Groundbreaking PCIe 7.0 Demos

As we move through 2025, the momentum generated by Cadence continues to energize…

• 2 min read
Design IP , PCIe 7.0 , PCIe , PCI-SIG

Learning and Support

Analog and Digital IC Design Flows: The Past, Present, and Future of Electronics

Curious to see how your IC design skills (Analog/Digital) stack up—or where to level…

• 8 min read
college grads , digital design , blended training , AIML , specifications , xcellium , Custom IC flow , onboarding , Genus , Analog IC Flow , schematic design , GDSII , chip design , Tempus , pegasus , ASIC flow , RTL , video , Self Learning , tutorial , 3DIC , Cadence Online Support , APR , Digital IC Flow , Virtuoso ADE , place and route , Cadence training , digital badges , learninggap , training bytes , Virtuoso , Design and Verification , Semiconductor , Spectre , learnfast , Post Layout , Digital Implementation , GenAI , Innovus , physical design , Layout design , mobile , Virtuoso Layout , learning and support , Pre Layout , Verisium Manager , Quantus , online training , simulation , silicon , Digital Physical Design , Tape-out

Digital Design

Elevate Your EDA Skills: Achieve Unmatched PPA with Genus Synthesis Solution

As the electronic design automation (EDA) landscape continues to evolve, the importance…

• 4 min read
training , training bytes , Optimize , Genus Synthesis Solution , Synthesis , online training

System, PCB, & Package Design 

Discover Cadence Community Forums Resources for Tcl Scripting

In the world of PCB design and IC packaging, automation is key to enhancing productivity…

• 2 min read
PCB , Allegro X AI , cadence , awr , Tcl Scripting , Cadence Community Forums , community forum , SPB , PCB design

Corporate News

Driving the Future of High-Speed Computing with PCIe 7.0 Innovation

Escalating compute processing demands from generative and agentic AI applications…

• 4 min read
controller IP , Verification IP , featured , agentic ai , PHY , PCIe 7.0 , PCIe , HPC , high-performance computing , PCI-SIG

Digital Design

Transforming Chip Design with Cadence Cerebrus AI Studio

Cadence is transforming chip design with the launch of Cadence Cerebrus ® AI Studio…

• 1 min read
digital design , featured , agentic ai , designed with cadence , Cadence Cerebrus , Digital Implementation , AI

Cadence Japan

ケイデンスのエージェント型AIがSoC/システム・エンジニアリングの時間を数ヶ月短縮

最新のSoC設計の複雑さに対応するにあたり、AIを活用したチップ設計は必要不可欠となっています。設計に活用するエージェント型AIの段階、ケイデンスの関連製品などについては…

• less than a min read
news story , SoC , japanese blog , AI

SoC and IP

Time-of-Flight Decoding with Tensilica Vision DSPs - AI's Role in ToF Decoding

In our previous blog, we discussed the fundamentals of time-of-flight (ToF) technology…

• 5 min read
IP , vision processing , IoT , Tensilica DSPs , ip cores , Vision DSPs , Tensilica , vision , semiconductor IP , imaging , image processing

Verification

Insights from the Verification Software Track at CadenceLIVE Silicon Valley 2025

Earlier this month, I had the opportunity to attend CadenceLIVE Silicon Valley 2025…

• 2 min read
Verification IP , SVG , software , cadencelive , SimAI , xcelium , verification
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